Electrical test structures and measurement techniques for the characterisation of advanced photomasks

Existing photomask metrology is struggling to keep pace with the rapid reduction of IC dimensions as traditional measurement techniques are being stretched to their limits. This thesis examines the use of on-mask probable electrical test structures and measurement techniques to meet this challenge and to accurately characterise the imaging capabilities of advanced binary and phase-shifting chrome-on-quartz photomasks. On-mask, electrical and optical linewidth measurement techniques have highlighted that the use of more than one measurement method, complementing each other, can prove valuable when characterising an advanced photomask process. Industry standard optical metrology test patterns have been adapted for the direct electrical equivalent measurement and the structures used to characterise different feature arrangements fabricated on standard and advanced photomasks with proximity correction techniques. The electrical measurements were compared to measurements from an optical mask metrology and verification tool and a state-of-the-art CD-AFM system and the results have demonstrated the capability and strengths of the on-mask electrical measurement. For example, electrical and AFM measurements on submicron features agreed within 10nm of each other while optical measurements were offset by up to 90nm. Hence, electrical techniques can prove valuable in providing feedback to the large number of metrology tools already supporting photomask manufacture, which in turn will help to develop CD standards for maskmaking. Electrical test structures have also been designed to enable the characterisation of optical proximity correction to characterise right angled corners in conducting tracks using a prototype design for both on-mask and wafer characterisation. Measurement results from the on-mask structures have shown that the electrical technique is sensitive enough to detect the effect of OPC on inner corners and to identify any defects in the fabricated features. For example less than 10 (5%) change in the expected resistance data trends indicated a deformed OPC feature. Results from on-wafer structures have shown that the correction technique has an impact on the final printed features and the measured resistance can be used to characterise the effects of different levels of correction. Overall the structures have shown their capability to characterise this type of optical proximity correction on both mask and wafer level. Test structures have also been designed for the characterisation of the dimensional mismatch between closely spaced photomask features. A number of photomasks were fabricated with these structures and the results from electrical measurements have been analysed to obtain information about the capability of the mask making process. The electrical test structures have demonstrated the capability of measuring tool and process induced dimensional mismatches in the nanometer range on masks which would otherwise prove difficult with standard optical metrology techniques. For example, electrical measurements detected mismatches of less than 15nm on 500nm wide features

Die-Level Thinning for Flip-Chip Integration on Flexible Substrates

Die-level thinning, handling, and integration of singulated dies from multi-project wafers (MPW) are often used in research, early-stage development, and prototyping of flexible devices. There is a high demand for thin silicon devices for several applications, such as flexible electronics. To address this demand, we study a novel post-processing method on two silicon devices, an electrochemical impedance sensor, and Complementary Metal Oxide Semiconductor (CMOS) die. Both are drawn from an MPW batch, thinned at die-level after dicing and singulation down to 60 µm. The thinned dies were flip-chip bonded to flexible substrates and hermetically sealed by two techniques: thermosonic bonding of Au stud bumps and anisotropic conductive paste (ACP) bonding. The performance of the thinned dies was assessed via functional tests and compared to the original dies. Furthermore, the long-term reliability of the flip-chip bonded thinned sensors was demonstrated to be higher than the conventional wire-bonded sensors

A Low Cost Patternable Packaging Technology for Biosensors

This paper demonstrates a simple and low cost technology to reliably and accurately package integrated chips. Microchannels and cavities of minimum feature size of 500 μm can be reliably reproduced. In addition, the curing depth in relation to the exposure time was investigated. A simple microfluidic device, consisting of a 500 μm channel and 2 mm ports, was manufactured to demonstrate the possibilities of this technology. Extensive electrochemical experiments showed that the packaging material is a good insulator and leaves no residue on the chip

Test Structures for Developing Packaging for Implantable Sensors

With their capacity for real time monitoring and spatial mapping, implantable sensors are becoming an increasingly important aspect of next generation precision healthcare. Microfabricated sensor systems are a popular choice, owing to their capacity for miniaturisation, repeatable mass manufacture, and numerous pre-existing sensor archetypes. Despite the drive for development, packaging these sensors for the environment within the body, as well as the implantation process itself, presents a significant challenge. This paper presents microelectronic test structures, which can be used to assess, compare, and optimise implantable packaging solutions in a standardised manner. The proposed structures are used to investigate: (i) the capacity of the material to be patterned, (ii) the permeability of the insulation material, (iii) adhesion of the encapsulant to the die, and (iv) the physical robustness of the package to implantation through a needle. They are used to characterise an example packaging strategy, using biocompatible epoxy-resin. In addition, a method of optimising the packaging performance using the test structures is presented